VL

Vitaly Lagoon

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
CI Cadence Design (Israel) Ii: 1 patents #3 of 8Top 40%
VE Verisity: 1 patents #5 of 7Top 75%
📍 Melbourne, MA: #19 of 24 inventorsTop 80%
Overall (All Time): #1,229,228 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
8560893 Systems and methods for automatically generating executable system level-tests from a partially specified scenario Yoav Hollander, Efrat Gavish, Matan Vax 2013-10-15
7870523 System and method for test generation with dynamic constraints using static analysis and multidomain constraint reduction Shlomi Uziel, Amos Noy, Yael Kinderman, Amit Gal 2011-01-11
7613973 Method for providing bitwise constraints for test generation Guy Baruch 2009-11-03
6918076 Method for providing bitwise constraints for test generation Guy Barruch 2005-07-12