YH

Yoav Hollander

VE Verisity: 5 patents #1 of 7Top 15%
CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
CI Cadence Design (Israel) Ii: 1 patents #3 of 8Top 40%
Overall (All Time): #490,172 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11999366 System and methods thereof for monitoring proper behavior of an autonomous vehicle Oded Doron HIRSCHFELD, Yaron Kashai 2024-06-04
9208271 Transaction correlation system Reshef Meir, Yael Kinderman, Ohad Givaty 2015-12-08
8560893 Systems and methods for automatically generating executable system level-tests from a partially specified scenario Efrat Gavish, Vitaly Lagoon, Matan Vax 2013-10-15
8302050 Automatic debug apparatus and method for automatic debug of an integrated circuit design Yael Feldman 2012-10-30
7665067 Method and system for automatically creating tests Yaron Kashai 2010-02-16
7284177 Method and apparatus for functionally verifying a physical device under test Yaron Kashai 2007-10-16
6675138 System and method for measuring temporal coverage detection Lev Plotnikov, Yaron Kashai 2004-01-06
6530054 Method and apparatus for test generation during circuit design 2003-03-04
6347388 Method and apparatus for test generation during circuit design 2002-02-12
6182258 Method and apparatus for test generation during circuit design 2001-01-30