Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9064063 | Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints | Henry Yu, Joshua Baudhuin, Regis Colwell, Harsh Deshmane, Elias Lee Fallon +8 more | 2015-06-23 |
| 9026958 | Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout | Sanjib Ghosh, Henry Yu | 2015-05-05 |
| 8839183 | Method and apparatus for derived layers visualization and debugging | Pardeep Juneja, Sanjiib Ghosh | 2014-09-16 |
| 8813006 | Accelerated characterization of circuits for within-die process variations | Sachin Shrivastava | 2014-08-19 |
| 8711177 | Generation, display, and manipulation of measurements in computer graphical designs | Chayan Majumder, Donald J. O'Riordan | 2014-04-29 |
| 8694943 | Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness | Henry Yu, Roland Ruehl, Elias Lee Fallon, Regis Colwell, Joshua Baudhuin +8 more | 2014-04-08 |
| 8612199 | Netlist partitioning for characterizing effect of within-die variations | Sachin Shrivastava | 2013-12-17 |
| 8555237 | Method and apparatus for design rule violation reporting and visualization | Pardeep Juneja, Om Kanwar | 2013-10-08 |
| 8086983 | Method and system for performing improved timing window analysis | Sachin Shrivastava | 2011-12-27 |