Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8001512 | Method and system for implementing context simulation | — | 2011-08-16 |
| 8001516 | Characterization and reduction of variation for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2011-08-16 |
| 7962866 | Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs | Louis K. Scheffer | 2011-06-14 |
| 7962867 | Electronic design for integrated circuits based on process related variations | Taber H. Smith | 2011-06-14 |
| 7937674 | Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs | Louis K. Scheffer | 2011-05-03 |
| 7861203 | Method and system for model-based routing of an integrated circuit | Eric Nequist | 2010-12-28 |
| 7853904 | Method and system for handling process related variations for integrated circuits based upon reflections | — | 2010-12-14 |
| 7827519 | Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs | Louis K. Scheffer | 2010-11-02 |
| 7814447 | Supplant design rules in electronic designs | Louis K. Scheffer | 2010-10-12 |
| 7774726 | Dummy fill for integrated circuits | — | 2010-08-10 |
| 7757195 | Methods and systems for implementing dummy fill for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2010-07-13 |
| 7725845 | System and method for layout optimization using model-based verification | Roland Ruehl, Eric Nequist | 2010-05-25 |
| 7721237 | Method, system, and computer program product for timing closure in electronic designs | Louis K. Scheffer | 2010-05-18 |
| 7712056 | Characterization and verification for integrated circuit designs | Taber H. Smith | 2010-05-04 |
| 7707528 | System and method for performing verification based upon both rules and models | Roland Ruehl, Mathew Koshy | 2010-04-27 |
| 7689948 | System and method for model-based scoring and yield prediction | Roland Ruehl, Mathew Koshy | 2010-03-30 |
| 7393755 | Dummy fill for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2008-07-01 |
| 7383521 | Characterization and reduction of variation for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2008-06-03 |
| 7380220 | Dummy fill for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2008-05-27 |
| 7367008 | Adjustment of masks for integrated circuit fabrication | Taber H. Smith | 2008-04-29 |
| 7363099 | Integrated circuit metrology | Taber H. Smith | 2008-04-22 |
| 7363598 | Dummy fill for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2008-04-22 |
| 7360179 | Use of models in integrated circuit fabrication | Taber H. Smith, Vikas Mehrotra | 2008-04-15 |
| 7356783 | Dummy fill for integrated circuits | Taber H. Smith, Vikas Mehrotra | 2008-04-08 |
| 7353475 | Electronic design for integrated circuits based on process related variations | Taber H. Smith | 2008-04-01 |