DW

David White

CS Cadence Design Systems: 45 patents #7 of 2,263Top 1%
Google: 2 patents #10,498 of 22,993Top 50%
PR Promed: 1 patents #10 of 19Top 55%
General Motors: 1 patents #9,361 of 18,328Top 55%
📍 San Jose, CA: #807 of 32,062 inventorsTop 3%
🗺 California: #6,736 of 386,348 inventorsTop 2%
Overall (All Time): #45,755 of 4,157,543Top 2%
55
Patents All Time

Issued Patents All Time

Showing 51–55 of 55 patents

Patent #TitleCo-InventorsDate
7325206 Electronic design for integrated circuits based process related variations Taber H. Smith 2008-01-29
7243316 Test masks for lithographic and etch processes Taber H. Smith 2007-07-10
7174520 Characterization and verification for integrated circuit designs Taber H. Smith 2007-02-06
7152215 Dummy fill for integrated circuits Taber H. Smith, Vikas Mehrotra 2006-12-19
7124386 Dummy fill for integrated circuits Taber H. Smith, Vikas Mehrotra 2006-10-17