AS

Ankush Sood

CS Cadence Design Systems: 6 patents #235 of 2,263Top 15%
Overall (All Time): #847,938 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
9411912 Clock topology planning for reduced power consumption Aaron Paul Hurst 2016-08-09
9280614 Methods, systems, and apparatus for clock topology planning with reduced power consumption Aaron Paul Hurst 2016-03-08
9135375 Methods for construction and optimization of a clock tree plan for reduced power consumption Aaron Paul Hurst 2015-09-15
8826211 Graphical user interface for physically aware clock tree planning Aaron Paul Hurst 2014-09-02
8782591 Physically aware logic synthesis of integrated circuit designs Tsuwei Ku, David John Seibert, Huey-Yih Wang, Hua Song, Kai Zhu +1 more 2014-07-15
7774735 Integrated circuit netlist migration 2010-08-10