TK

Tsuwei Ku

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 Cupertino, CA: #4,039 of 6,989 inventorsTop 60%
🗺 California: #185,134 of 386,348 inventorsTop 50%
Overall (All Time): #2,020,925 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8935651 Methods and apparatus for data path cluster optimization Samir Agrawal, Jean-Charles Giomi 2015-01-13
8782591 Physically aware logic synthesis of integrated circuit designs David John Seibert, Huey-Yih Wang, Hua Song, Kai Zhu, Yu-Fang Chung +1 more 2014-07-15