Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10283407 | Two-dimensional self-aligned super via integration on self-aligned gate contact | Ruilong Xie | 2019-05-07 |
| 10263099 | Self-aligned finFET formation | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2019-04-16 |
| 10242881 | Self-aligned single dummy fin cut with tight pitch | Kangguo Cheng, Chi-Chun Liu, Peng Xu | 2019-03-26 |
| 10170591 | Self-aligned finFET formation | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2019-01-01 |
| 10157827 | Semiconductor contact | Ruilong Xie | 2018-12-18 |
| 10157798 | Uniform bottom spacers in vertical field effect transistors | Min Gyu Sung, Ruilong Xie, Tenko Yamashita | 2018-12-18 |
| 10109533 | Nanosheet devices with CMOS epitaxy and method of forming | Ruilong Xie, Pietro Montanini, Tenko Yamashita, Nicolas Loubet | 2018-10-23 |
| 10084068 | Self-aligned finFET formation | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2018-09-25 |
| 9997403 | Metal layer tip to tip short | Ruilong Xie | 2018-06-12 |
| 9947548 | Self-aligned single dummy fin cut with tight pitch | Kangguo Cheng, Chi-Chun Liu, Peng Xu | 2018-04-17 |
| 9929020 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2018-03-27 |
| 9887133 | Two-dimensional self-aligned super via integration on self-aligned gate contact | Ruilong Xie | 2018-02-06 |
| 9837402 | Method of concurrently forming source/drain and gate contacts and related device | Ruilong Xie | 2017-12-05 |
| 9786557 | Two-dimensional self-aligned super via integration on self-aligned gate contact | Ruilong Xie | 2017-10-10 |
| 9589847 | Metal layer tip to tip short | Ruilong Xie | 2017-03-07 |
| 9536750 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2017-01-03 |
| 9129865 | Display panel and driving method thereof | — | 2015-09-08 |