Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8966429 | Bit slice elements utilizing through device routing | Andrew M. Havlir, James DeLeon | 2015-02-24 |
| 8953395 | Memory with variable strength sense amplifier | Michael E. Runas | 2015-02-10 |
| 8947120 | Latch array utilizing through device connectivity | Gregory D. Roberts, Robert D. Kenney, James De Leon | 2015-02-03 |
| 8780654 | Weak bit detection in a memory through variable development time | Michael E. Runas | 2014-07-15 |
| 8780650 | Memory with redundant sense amplifier | Michael E. Runas | 2014-07-15 |
| 8780657 | Memory with bit line current injection | Michael E. Runas | 2014-07-15 |
| 8677199 | Pulse dynamic logic gates with mux-D scan functionality | Michael E. Runas | 2014-03-18 |
| 8559249 | Memory with redundant sense amplifier | Michael E. Runas | 2013-10-15 |
| 8555121 | Pulse dynamic logic gates with LSSD scan functionality | Michael E. Runas | 2013-10-08 |
| 8482315 | One-of-n N-nary logic implementation of a storage cell | Raymond Cheung Yeung | 2013-07-09 |
| 8450991 | Charge recycling a 1 of N NDL gate with a time varying power supply | Michael E. Runas | 2013-05-28 |
| 6956406 | Static storage element for dynamic logic | Terence M. Potter, James S. Blomgren | 2005-10-18 |
| 6911846 | Method and apparatus for a 1 of N signal | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Anthony M. Petro | 2005-06-28 |
| 6745357 | Dynamic logic scan gate method and apparatus | David W. Chrudimsky, Stephen C. Horne, James S. Blomgren | 2004-06-01 |
| 6571378 | Method and apparatus for a N-NARY logic circuit using capacitance isolation | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Anthony M. Petro | 2003-05-27 |
| 6415405 | Method and apparatus for scan of synchronized dynamic logic using embedded scan gates | Stephen C. Horne, James S. Blomgren | 2002-07-02 |
| 6271683 | Dynamic logic scan gate method and apparatus | Stephen C. Horne, James S. Blomgren | 2001-08-07 |
| 6252425 | Method and apparatus for an N-NARY logic circuit | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Anthony M. Petro | 2001-06-26 |
| 6211456 | Method and apparatus for routing 1 of 4 signals | James S. Blomgren, Terence M. Potter | 2001-04-03 |
| 6202194 | Method and apparatus for routing 1 of N signals | James S. Blomgren, Terence M. Potter | 2001-03-13 |
| 6181596 | Method and apparatus for a RAM circuit having N-Nary output interface | Stephen C. Horne, James S. Blomgren | 2001-01-30 |
| 6124735 | Method and apparatus for a N-nary logic circuit using capacitance isolation | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Anthony M. Petro | 2000-09-26 |
| 6118716 | Method and apparatus for an address triggered RAM circuit | Stephen C. Horne, James S. Blomgren | 2000-09-12 |
| 6115294 | Method and apparatus for multi-bit register cell | James S. Blomgren, Terence M. Potter, Stephen C. Horne | 2000-09-05 |
| 6107835 | Method and apparatus for a logic circuit with constant power consumption | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Anthony M. Petro | 2000-08-22 |