Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
JB

Joseph P. Bratt

Apple: 58 patents #446 of 18,612Top 3%
SGSilicon Graphics: 4 patents #100 of 758Top 15%
San Jose, CA: #657 of 32,062 inventorsTop 3%
California: #5,467 of 386,348 inventorsTop 2%
Overall (All Time): #36,489 of 4,157,543Top 1%
62 Patents All Time

Issued Patents All Time

Showing 51–62 of 62 patents

Patent #TitleCo-InventorsDate
6771264 Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor Jerome F. Duluk, Jr., Stephen L. Dodgen, Matthew Nicholas Papakipos, Nathan Tuck, Richard E. Hessel 2004-08-03
6717576 Deferred shading graphics pipeline processor having advanced features Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, George Cuan +19 more 2004-04-06
6697076 Method and apparatus for address re-mapping Sushma S. Trivedi 2004-02-24
6693639 Graphics processor with pipeline state storage and retrieval Jerome F. Duluk, Jr., Jack Benkual, Shun Wai Go, Sushma S. Trivedi, Richard E. Hessel 2004-02-17
6597363 Graphics processor with deferred shading Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, George Cuan +11 more 2003-07-22
6525737 Graphics processor with pipeline state storage and retrieval Jerome F. Duluk, Jr., Jack Benkual, Shun Wai Go, Sushma S. Trivedi, Richard E. Hessel 2003-02-25
6268875 Deferred shading graphics pipeline processor Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, George Cuan +11 more 2001-07-31
6229553 Deferred shading graphics pipeline processor Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, George Cuan +11 more 2001-05-08
5740402 Conflict resolution in interleaved memory systems with multiple parallel accesses John F. Brennen, Peter Hsu, Joseph T. Scanlon, Man Kit Tang, Steven J. Ciavaglia 1998-04-14
5632025 Method for preventing multi-level cache system deadlock in a multi-processor system John Brennan, Peter Hsu, William A. Huffman, Joseph T. Scanlon, Steve J. Ciavaglia 1997-05-20
5572704 System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes John Brennan, Peter Hsu, William A. Huffman, Joseph T. Scanlon, Steve Ciavagia 1996-11-05
5537538 Debug mode for a superscalar RISC processor John Brennan, Peter Hsu, Chandra Joshi, William A. Huffman, Monica R. Nofal +3 more 1996-07-16