Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9182811 | Interfacing dynamic hardware power managed blocks and software power managed blocks | Gurjeet S. Saund, Munetoshi Fukami, Shane J. Keil, Chaitanya Kosaraju, Erdem Guleyupoglu +2 more | 2015-11-10 |
| 9152588 | Race-free level-sensitive interrupt delivery using fabric delivered interrupts | Manu Gulati, Deniz Balkan | 2015-10-06 |
| 9152210 | Method and apparatus for determining tunable parameters to use in power and performance management | Brian P. Lilly, Gurjeet S. Saund, Sukalpa Biswas | 2015-10-06 |
| 9081517 | Hardware-based automatic clock gating | Kleanthes G. Koniaris, Josh P. de Cesare, Timothy J. Millet, Jung Wook Cho | 2015-07-14 |
| 9081556 | Power on reset detector | Timothy R. Paaske | 2015-07-14 |
| 9043632 | Security enclave processor power control | Manu Gulati, Josh P. de Cesare | 2015-05-26 |
| 9032104 | Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling | Moshe B. Simon, David Harrison | 2015-05-12 |
| 9024699 | Numerically-controlled oscillator | Kleanthes G. Koniaris, Shane J. Keil | 2015-05-05 |
| 9009377 | Edge-triggered interrupt conversion in a system employing level-sensitive interrupts | Deniz Balkan, Manu Gulati | 2015-04-14 |
| 8963587 | Clock generation using fixed dividers and multiplex circuits | Raman S. Thiara, Shane J. Keil, Timothy J. Millet | 2015-02-24 |
| 8959270 | Interrupt distribution scheme | Josh P. de Cesare, Ruchi Wadhawan, Mark D. Hayter | 2015-02-17 |
| 8867533 | Multi-tier switch interface unit arbiter | — | 2014-10-21 |
| 8806232 | Systems and method for hardware dynamic cache power management via bridge and power manager | Timothy J. Millet, Deniz Balkan, Vijay Gupta | 2014-08-12 |
| 8806245 | Memory read timing margin adjustment for a plurality of memory arrays according to predefined delay tables | Michael Frank | 2014-08-12 |
| 8799715 | System on a chip (SOC) debug controllability | Manu Gulati, James D. Ramsay, Jianlin Yu | 2014-08-05 |
| 8786332 | Reset extender for divided clock domains | David S. Warren, Shane J. Keil, Sukalpa Biswas | 2014-07-22 |
| 8681526 | Size and retry programmable multi-synchronous FIFO | Moshe B. Simon, Mark Longley | 2014-03-25 |
| 8645743 | Mechanism for an efficient DLL training protocol during a frequency change | Hao Chen, Sanjay Mansingh | 2014-02-04 |
| 8468373 | Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state | Timothy J. Millet, Josh P. de Cesare | 2013-06-18 |
| 8417983 | Adjusting a device clock source to reduce wireless communication interference | Timothy J. Millet, Stephan V. Schell | 2013-04-09 |
| 8310291 | DLL having a different training interval during a voltage change | James D. Ramsay, Sanjay Mansingh | 2012-11-13 |
| 8190942 | Method and system for distributing a global timebase within a system-on-chip having multiple clock domains | Moshe B. Simon | 2012-05-29 |
| 8151008 | Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling | Moshe B. Simon, David Harrison | 2012-04-03 |
| 8120377 | Integrated circuit having secure access to test modes | Jianlin Yu, Michael Frank, Jerrold V. Hauck, Jean-Didier Allegrucci, Santiago Fernandez-Gomez | 2012-02-21 |
| 7716269 | Method and system for performing parallel integer multiply accumulate operations on packed data | Moshe B. Simon, David Harrison, Rakesh Singh | 2010-05-11 |