WJ

William M. Johnson

AM AMD: 41 patents #198 of 9,279Top 3%
DL Draper Laboratory: 13 patents #33 of 921Top 4%
IBM: 11 patents #9,995 of 70,183Top 15%
UN Unknown: 10 patents #823 of 83,584Top 1%
MT Mireplica Technology: 6 patents #1 of 2Top 50%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
TI Texas Instruments: 1 patents #7,357 of 12,488Top 60%
🗺 Texas: #691 of 125,132 inventorsTop 1%
Overall (All Time): #22,217 of 4,157,543Top 1%
81
Patents All Time

Issued Patents All Time

Showing 26–50 of 81 patents

Patent #TitleCo-InventorsDate
5867683 Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations David B. Witt 1999-02-02
5867682 High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations David B. Witt 1999-02-02
5848287 Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches Thang M. Tran, David B. Witt 1998-12-08
5845101 Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache Thang M. Tran, Matt T. Gavin, Mike Pedneau 1998-12-01
5835744 Microprocessor configured to swap operands in order to minimize dependency checking logic Thang M. Tran, David B. Witt 1998-11-10
5828869 Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism David B. Witt 1998-10-27
5805912 Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor David B. Witt 1998-09-08
5787266 Apparatus and method for accessing special registers without serialization Thang M. Tran, Rupaka Mahalingaiah 1998-07-28
5761137 DRAM access system and method Thang M. Tran, Stephen C. Kromer 1998-06-02
5758114 High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor David B. Witt, Thang M. Tran 1998-05-26
5751981 High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format David B. Witt 1998-05-12
RE35794 System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache 1998-05-12
5664136 High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations David B. Witt 1997-09-02
5655097 High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format David B. Witt 1997-08-05
5655098 High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format David B. Witt 1997-08-05
5651125 High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations David B. Witt 1997-07-22
5574928 Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments Scott White, Michael D. Goddard 1996-11-12
5557347 Ballistic missile boresight and inertial tracking system and method 1996-09-17
5546309 Apparatus and method for autonomous satellite attitude sensing Howard Musoff 1996-08-13
5544843 Ballistic missile remote targeting system and method 1996-08-13
5360184 High-performance, low-cost inertial guidance system 1994-11-01
5357626 Processing system for providing an in circuit emulator with processor internal state David B. Witt 1994-10-18
5317715 Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics Timothy A. Olson, Drew J. Dutton, Sherman Lee, David W. Stoenner 1994-05-31
5247644 Processing system with improved sequential memory accessing David B. Witt 1993-09-21
5237700 Exception handling processor for handling first and second level exceptions with reduced exception latency Michael D. Goddard, Tim Olson 1993-08-17