Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8629711 | Precise control component for a substarate potential regulation circuit | — | 2014-01-14 |
| 8436675 | Feedback-controlled body-bias voltage source | — | 2013-05-07 |
| 8350616 | Variable output charge pump circuit | Robert Fu | 2013-01-08 |
| 8193852 | Precise control component for a substrate potential regulation circuit | — | 2012-06-05 |
| 8085084 | System for substrate potential regulation during power-up in integrated circuits | Robert Fu | 2011-12-27 |
| 8022747 | System for substrate potential regulation during power-up in integrated circuits | Robert Fu | 2011-09-20 |
| 7847619 | Servo loop for well bias voltage source | — | 2010-12-07 |
| 7791880 | Fan and plug thereof | Te-Tsai Chuang | 2010-09-07 |
| 7786756 | Method and system for latchup suppression | Vjekoslav Svilan, Kleanthes G. Koniaris, James B. Burr | 2010-08-31 |
| 7719344 | Stabilization component for a substrate potential regulation circuit | Robert Fu | 2010-05-18 |
| 7692477 | Precise control component for a substrate potential regulation circuit | — | 2010-04-06 |
| 7649402 | Feedback-controlled body-bias voltage source | — | 2010-01-19 |
| 7642835 | System for substrate potential regulation during power-up in integrated circuits | Robert Fu | 2010-01-05 |
| 7597571 | Fan and plug thereof | Te-Tsai Chuang | 2009-10-06 |
| 7362165 | Servo loop for well bias voltage source | — | 2008-04-22 |
| 7129771 | Servo loop for well bias voltage source | — | 2006-10-31 |
| 7012461 | Stabilization component for a substrate potential regulation circuit | Robert Fu | 2006-03-14 |
| 6359808 | Low voltage read cascode for 2V/3V and different bank combinations without metal options for a simultaneous operation flash memory device | Kazuhiro Kurihara, Takao Akaogi | 2002-03-19 |
| 6327194 | Precise reference wordline loading compensation for a high density flash memory device | Kazuhiro Kurihara | 2001-12-04 |
| 6327181 | Reference cell bitline path architecture for a simultaneous operation flash memory device | Takao Akaogi, Kazuhiro Kurihara | 2001-12-04 |
| 6285585 | Output switching implementation for a flash memory device | Kazuhiro Kurihara | 2001-09-04 |
| 6275421 | Chip enable input buffer | Kazuhiro Kurihara | 2001-08-14 |
| 6266284 | Output buffer for external voltage | Kazuhiro Kurihara | 2001-07-24 |
| 6259645 | Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory | Ming-Huei Shieh | 2001-07-10 |
| 6259633 | Sense amplifier architecture for sliding banks for a simultaneous operation flash memory device | Kazuhiro Kurihara, Takao Akaogi | 2001-07-10 |