Issued Patents All Time
Showing 51–75 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6816593 | Method and apparatus for transposing bits | DeForest Tovey | 2004-11-09 |
| 6775414 | Variable-length code decoder | Chad Fogg, Nital Patwa, Parin Bhadrik Dalal, Korbin S. Van Dyke, Steve C. Hale | 2004-08-10 |
| 6763452 | Modifying program execution based on profiling | Paul H. Hohensee, John S. Yates, Jr., Korbin S. Van Dyke, David L. Reese | 2004-07-13 |
| 6745318 | Method and apparatus of configurable processing | Sanjay Mansingh, Niteen A. Patkar, Korbin S. Van Dyke, Stephen C. Hale, Dee Tovey +1 more | 2004-06-01 |
| 6643726 | Method of manufacture and apparatus of an integrated computing system | Niteen A. Patkar, Ali Alasti, Don A. Van Dyke, Korbin S. Van Dyke, Shalesh Thusoo +1 more | 2003-11-04 |
| 6460065 | Circuit and method for partial product bit shifting | — | 2002-10-01 |
| 6449671 | Method and apparatus for busing data elements | Niteen A. Patkar, Shalesh Thusoo, Korbin S. Van Dyke | 2002-09-10 |
| 6430646 | Method and apparatus for interfacing a processor with a bus | Shalesh Thusoo, Niteen A. Patkar, Korbin S. Van Dyke | 2002-08-06 |
| 6415311 | Sign extension circuit and method for unsigned multiplication and accumulation | Nital Patwa | 2002-07-02 |
| 6393453 | Circuit and method for fast squaring | — | 2002-05-21 |
| 6286023 | Partitioned adder tree supported by a multiplexer configuration | Nital Patwa | 2001-09-04 |
| 6249799 | Selective carry boundary | Nital Patwa | 2001-06-19 |
| 6199090 | Double incrementing, low overhead, adder | Sanjay Mansingh | 2001-03-06 |
| 6167422 | Booth multiplication structure which selectively integrates the function of either of incrementing or negating with the function of booth multiplication | Nital Patwa | 2000-12-26 |
| 6127842 | Modified adder tree structure and method using logic and gates to generate carry-in values | Parin Bhadrik Dalal, Steve C. Hale, Nital Patwa | 2000-10-03 |
| 6122442 | Structure and method for motion estimation of a digital image by matching derived scores | Didier J. Le Gall | 2000-09-19 |
| 6081823 | Circuit and method for wrap-around sign extension for signed numbers | Nital Patwa | 2000-06-27 |
| 6073156 | Circuit and method for wrap-around sign extension for signed numbers using replacement of most significant bit | Nital Patwa | 2000-06-06 |
| 6071004 | Non-linear digital filters for interlaced video signals and method thereof | Didier J. Le Gall | 2000-06-06 |
| 5910909 | Non-linear digital filters for interlaced video signals and method thereof | Didier J. Le Gall | 1999-06-08 |
| 5870497 | Decoder for compressed video signals | David E. Galbi, Eric Chi-Wang Chai | 1999-02-09 |
| 5864704 | Multimedia processor using variable length instructions with opcode specification of source operand as result of prior instruction | James T. Battle, Andy Hung | 1999-01-26 |
| 5815646 | Decompression processor for video applications | David E. Galbi, Frank H. Liao, Yvonne C. Tse | 1998-09-29 |
| 5812437 | Programmable logic unit for arithmetic, logic and equality functions | John Thomson | 1998-09-22 |
| 5809174 | Decompression processor for video applications | David E. Galbi, Frank H. Liao, Yvonne C. Tse | 1998-09-15 |