Issued Patents All Time
Showing 76–100 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10282308 | Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems | Andrew G. Kegel | 2019-05-07 |
| 10268416 | Method and systems of controlling memory-to-memory copy operations | David A. Roberts | 2019-04-23 |
| 10242420 | Preemptive context switching of processes on an accelerated processing device (APD) based on time quanta | Robert Scott Hartog, Ralph C. Taylor, Michael Mantor, Kevin J. McGrath, Sebastien Nussbaum +4 more | 2019-03-26 |
| 10198369 | Dynamic memory remapping to reduce row-buffer conflicts | Yasuko Eckert, Reena Panda | 2019-02-05 |
| 10162757 | Proactive cache coherence | Yasuko Eckert | 2018-12-25 |
| 10133672 | System and method for efficient pointer chasing | Paula Aguilera Diez, Amin Farmahini-Farahani | 2018-11-20 |
| 10090236 | Interposer having a pattern of sites for mounting chiplets | David A. Roberts | 2018-10-02 |
| 10079044 | Processor with host and slave operating modes stacked with memory | Gabriel H. Loh, Bradford M. Beckmann, James M. O'Connor, Lisa R. Hsu | 2018-09-18 |
| 10049044 | Asynchronous cache flushing | Michael W. Boyer, Gabriel H. Loh | 2018-08-14 |
| 10042762 | Light-weight cache coherence for data processors with limited data sharing | Michael W. Boyer | 2018-08-07 |
| 10037267 | Instruction set architecture and software support for register state migration | Alexander D. Breslow, Dong Zhang | 2018-07-31 |
| 9977609 | Efficient accesses of data structures using processing near memory | Dong Zhang, Paula Aguilera Diez | 2018-05-22 |
| 9947386 | Thermal aware data placement and compute dispatch in a memory system | Manish Arora, Indrani Paul, Yasuko Eckert, Dong Zhang | 2018-04-17 |
| 9910605 | Page migration in a hybrid memory device | Gabriel H. Loh, James M. O'Connor, Niladrish Chatterjee | 2018-03-06 |
| 9875195 | Data distribution among multiple managed memories | Lisa R. Hsu, James M. O'Connor | 2018-01-23 |
| 9851777 | Power gating based on cache dirtiness | Manish Arora, Indrani Paul, Yasuko Eckert, Srilatha Manne, Madhu Saravana Sibi Govindan +1 more | 2017-12-26 |
| 9818455 | Query operations for stacked-die memory device | Gabriel H. Loh, James M. O'Connor, Yasuko Eckert | 2017-11-14 |
| 9804996 | Computation memory operations in a logic layer of a stacked memory | James M. O'Connor, Gabriel H. Loh, Michael Ignatowski, Michael Schulte | 2017-10-31 |
| 9792961 | Distributed computing with phase change material thermal management | Manish Arora, Gabriel H. Loh, Michael Schulte, Srilatha Manne | 2017-10-17 |
| 9755964 | Multi-protocol header generation system | David A. Roberts, Michael Ignatowski, Gabriel H. Loh | 2017-09-05 |
| 9720487 | Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration | William L. Bircher, Madhu Saravana Sibi Govindan, Manish Arora, Michael Schulte | 2017-08-01 |
| 9535831 | Page migration in a 3D stacked hybrid memory | Gabriel H. Loh, James M. O'Connor, Niladrish Chatterjee | 2017-01-03 |
| 9507632 | Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta | Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Kevin J. McGrath, Sebastien Nussbaum +4 more | 2016-11-29 |
| 9489321 | Scheduling memory accesses using an efficient row burst value | James M. O'Connor, Niladrish Chatterjee, Gabriel H. Loh | 2016-11-08 |
| 9471130 | Configuring idle states for entities in a computing device based on predictions of durations of idle periods | Manish Arora, Michael Schulte | 2016-10-18 |