Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5640573 | Power management message bus for integrated processor | James R. MacDonald | 1997-06-17 |
| 5632020 | System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking | Scott E. Swanstrom | 1997-05-20 |
| 5630099 | Non-volatile memory array controller capable of controlling memory banks having variable bit widths | James R. MacDonald | 1997-05-13 |
| 5625829 | Dockable computer system capable of symmetric multi-processing operations | Steven L. Belt, Drew J. Dutton | 1997-04-29 |
| 5623673 | System management mode and in-circuit emulation memory mapping and locking method | James R. MacDonald, Victor F. Andrade | 1997-04-22 |
| 5615207 | Side bus to dynamically off load main bus | Brett B. Stewart, Rita M. Wisor, Drew J. Dutton, Steven L. Belt | 1997-03-25 |
| 5598539 | Apparatus and method for achieving hot docking capabilities for a dockable computer system | Scott E. Swanstrom | 1997-01-28 |
| 5598537 | Apparatus and method for driving a bus to a docking safe state in a dockable computer system including a docking station and a portable computer | Scott E. Swanstrom | 1997-01-28 |
| 5561819 | Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller | Dan S. Mudgett, James R. MacDonald | 1996-10-01 |
| 5561821 | System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus | Dan S. Mudgett, James R. MacDonald | 1996-10-01 |
| 5557757 | High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus | Dan S. Mudgett, James R. MacDonald | 1996-09-17 |
| 5555430 | Interrupt control architecture for symmetrical multiprocessing system | Rupaka Mahalingaiah | 1996-09-10 |
| 5530891 | System management interrupt mechanism within a symmetrical multiprocessing system | — | 1996-06-25 |
| 5493684 | Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility | James R. MacDonald, Rita M. O'Brien | 1996-02-20 |
| 5404457 | Apparatus for managing system interrupt operations in a computing system | Andrew McBride | 1995-04-04 |
| 5388218 | Apparatus and method for supporting a transfer trapping discipline for a non-enabled peripheral unit within a computing system | Andrew McBride | 1995-02-07 |
| 5369777 | Integrated digital processing apparatus having a single biodirectional data bus for accommodating a plurality of peripheral devices connected to a plurality of external buses | James R. MacDonald, Govinda V. Kamath | 1994-11-29 |
| 5313597 | System for controlling communications among a computer processing unit and a plurality of peripheral devices | — | 1994-05-17 |
| 5218681 | Apparatus for controlling access to a data bus | James R. MacDonald | 1993-06-08 |
| 5175820 | Apparatus for use with a computing device controlling communications with a plurality of peripheral devices including a feedback bus to indicate operational modes | — | 1992-12-29 |
| 5060138 | Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus | Peggy Susan Howard Avalos | 1991-10-22 |