Issued Patents All Time
Showing 101–125 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10095421 | Hybrid memory module bridge network and buffers | — | 2018-10-09 |
| 10089221 | Systems and methods for memory system management based on information of a memory system | Robert M. Walker | 2018-10-02 |
| 10090236 | Interposer having a pattern of sites for mounting chiplets | Nuwan Jayasena | 2018-10-02 |
| 10079916 | Register files for I/O packet compression | Kevin Y. Cheng, Nathan Hu | 2018-09-18 |
| 10067872 | Memory speculation for multiple memories | — | 2018-09-04 |
| 10042750 | Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor | J. Thomas Pawlowski, Robert M. Walker | 2018-08-07 |
| 10019369 | Apparatuses and methods for pre-fetching and write-back for a segmented cache memory | J. Thomas Pawlowski | 2018-07-10 |
| 9983655 | Method and apparatus for performing inter-lane power management | Mitesh R. Meswani, Dmitri Yudanov, Arkaprava Basu, Sergey Blagodurov | 2018-05-29 |
| 9934148 | Memory module with embedded access metadata | Sergey Blagodurov | 2018-04-03 |
| 9811456 | Reliable wear-leveling for non-volatile memory and method therefor | — | 2017-11-07 |
| 9775182 | Wireless provisioning a device for a network using a soft access point | Yatharth Gupta | 2017-09-26 |
| 9769731 | Wireless network host in silent mode | Hui Shen, Christopher D. Gual, Anirban Banerjee, Yi Lu, John W. Archer +3 more | 2017-09-19 |
| 9767012 | Systems and methods for memory system management based on thermal information of a memory system | Robert M. Walker | 2017-09-19 |
| 9767028 | In-memory interconnect protocol configuration registers | Kevin Y. Cheng | 2017-09-19 |
| 9755964 | Multi-protocol header generation system | Michael Ignatowski, Nuwan Jayasena, Gabriel H. Loh | 2017-09-05 |
| 9727241 | Memory page access detection | Gabriel H. Loh, Mitesh R. Meswani, Mark Richard Nutter, John R. Slice, Prashant Jayaprakash Nair +1 more | 2017-08-08 |
| 9698790 | Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces | — | 2017-07-04 |
| 9639280 | Ordering memory commands in a computer system | — | 2017-05-02 |
| 9612972 | Apparatuses and methods for pre-fetching and write-back for a segmented cache memory | J. Thomas Pawlowski | 2017-04-04 |
| 9535627 | Latency-aware memory control | Michael Ignatowski | 2017-01-03 |
| 9504070 | Wireless provisioning a device for a network using a soft access point | Yatharth Gupta | 2016-11-22 |
| 9484113 | Error-correction coding for hot-swapping semiconductor devices | — | 2016-11-01 |
| 9477569 | Windows rally wireless HID device | Scott Manchester, Takeshi Nagao, Keiichi Kishi, Takeshi Misu, Yasuhiro Odagiri +1 more | 2016-10-25 |
| 9472299 | Methods and systems for mitigating memory drift | Michael Ignatowski | 2016-10-18 |
| 9443561 | Ring networks for intra- and inter-memory I/O including 3D-stacked memories | Yasuko Eckert, Mitesh R. Meswani, Indrani Paul | 2016-09-13 |