Issued Patents All Time
Showing 51–75 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11294747 | Self-regulating power management for a neural network system | Andrew G. Kegel | 2022-04-05 |
| 11281604 | Multiple memory type shared memory bus systems and methods | Joseph T. Pawlowski, Elliott C. Cooper-Balis | 2022-03-22 |
| 11275558 | Sorting instances of input data for processing through a neural network | — | 2022-03-15 |
| 11264079 | Apparatuses and methods for row hammer based cache lockdown | — | 2022-03-01 |
| 11237972 | Method and apparatus for controlling cache line storage in cache memory | — | 2022-02-01 |
| 11194728 | Memory-aware pre-fetching and cache bypassing systems and methods | — | 2021-12-07 |
| 11165749 | Assigning variable length address identifiers to packets in a processing system | — | 2021-11-02 |
| 11151043 | Demand delay and data value correlated memory pre-fetching systems and methods | — | 2021-10-19 |
| 11119908 | Systems and methods for memory system management | Robert M. Walker | 2021-09-14 |
| 11061572 | Memory object tagged memory monitoring method and system | Michael Ignatowski | 2021-07-13 |
| 11055150 | Fast thread wake-up through early lock release | Nuwan Jayasena, Amin Farmahini-Farahani | 2021-07-06 |
| 11023410 | Instructions for performing multi-line memory accesses | Shenghsun Cho | 2021-06-01 |
| 11012920 | Wireless network host in silent mode | Hui Shen, Christopher D. Gual, Anirban Banerjee, Yi Lu, John W. Archer +3 more | 2021-05-18 |
| 10990453 | Improving latency by performing early synchronization operations in between sets of program operations of a thread | Amin Farmahini-Farahani, Nuwan Jayasena | 2021-04-27 |
| 10970118 | Shareable FPGA compute engine | Andrew G. Kegel | 2021-04-06 |
| 10877894 | Memory-side transaction context memory interface systems and methods, wherein first context and first address are communicated on plural wires during different clock cycles and second context (of block of the first context) is communicated on additional wire during one of the different clock cycles | — | 2020-12-29 |
| 10877889 | Processor-side transaction context memory interface systems and methods | — | 2020-12-29 |
| 10862809 | Modifying carrier packets based on information in tunneled packets | — | 2020-12-08 |
| 10817412 | Methods for migrating information stored in memory using an intermediate depth map | J. Thomas Pawlowski, Robert M. Walker | 2020-10-27 |
| 10805392 | Distributed gather/scatter operations across a network of memory nodes | Amin Farmahini-Farahani | 2020-10-13 |
| 10713156 | Systems and methods for memory system management | Robert M. Walker | 2020-07-14 |
| 10684902 | Method and apparatus for memory vulnerability prediction | Vilas Sridharan | 2020-06-16 |
| 10672474 | High-performance on-module caching architectures for non-volatile dual in-line memory module (NVDIMM) | Amin Farmahini Farahani | 2020-06-02 |
| 10644004 | Utilizing capacitors integrated with memory devices for charge detection to determine DRAM refresh | Dmitri Yudanov | 2020-05-05 |
| 10599578 | Dynamic cache bypassing | Amin Farmahini Farahani | 2020-03-24 |