Issued Patents All Time
Showing 76–100 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6195749 | Computer system including a memory access controller for using non-system memory storage resources during system boot time | — | 2001-02-27 |
| 6167492 | Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system | James B. Keller, Larry D. Hewitt, Geoffrey S. Strongin | 2000-12-26 |
| 6151651 | Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system | Larry D. Hewitt | 2000-11-21 |
| 6148357 | Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes | Larry D. Hewitt | 2000-11-14 |
| 6134698 | Reduced pin count isochronous data bus | — | 2000-10-17 |
| 6122313 | Self-contained self-testing data modulator | Joe W. Peterson, Shin Saito, Masaru Nonogaki, Toshiaki Iimura | 2000-09-19 |
| 6101560 | Partitioned PC game port | — | 2000-08-08 |
| 6088748 | Personal computer system incorporating an isochronous multi-channel, multi-rate data bus | — | 2000-07-11 |
| 6085270 | Multi-channel, multi-rate isochronous data bus | — | 2000-07-04 |
| 6061802 | Software based clock synchronization | — | 2000-05-09 |
| 6058443 | System for partitioning PC chipset functions into logic and port integrated circuits | — | 2000-05-02 |
| 6044414 | System for preventing a DMA controller from evaluating its DRQ input once a DMA operation has started until the DRQ input has been updated | — | 2000-03-28 |
| 6032213 | PC core logic chipset comprising a serial register access bus | — | 2000-02-29 |
| 6012111 | PC chipset with integrated clock synthesizer | — | 2000-01-04 |
| 5999476 | Bios memory and multimedia data storage combination | Drew J. Dutton, Michael T. Wisor | 1999-12-07 |
| 5993057 | Apparatus for detecting and averaging data in a digital data stream | Satoru Maeda, Munehiro Yoshikawa, Manabu Oonishi | 1999-11-30 |
| 5987560 | Integrated programmable logic circuit for conditioning received input signals, detecting transitions of conditioned signals, and generating an associated interrupt respectively | — | 1999-11-16 |
| 5974492 | Method for input/output port replication using an interconnection bus | — | 1999-10-26 |
| 5958027 | Method and system for optimizing the flow of isochronous data and clock rate information | — | 1999-09-28 |
| 5944801 | Isochronous buffers for MMx-equipped microprocessors | — | 1999-08-31 |
| 5941976 | Interrupt request deassertion interlock mechanism | — | 1999-08-24 |
| 5926629 | Continuously operating interconnection bus | — | 1999-07-20 |
| 5898848 | Inter-chip bus structure for moving multiple isochronous data streams between integrated circuits | — | 1999-04-27 |
| 5898892 | Computer system with a data cache for providing real-time multimedia data to a multimedia engine | Andy Lambrecht, Mike Webb, Larry D. Hewitt, Brian C. Barnes | 1999-04-27 |
| 5870622 | Computer system and method for transferring commands and data to a dedicated multimedia engine | Andy Lambrecht, Mike Webb, Larry D. Hewitt, Brian C. Barnes | 1999-02-09 |