Issued Patents All Time
Showing 51–75 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651128 | Systems and methods for arbitrating between asynchronous and isochronous data for access to data transport resources | — | 2003-11-18 |
| 6631401 | Flexible probe/probe response routing for maintaining coherency | James B. Keller | 2003-10-07 |
| 6625743 | Method for synchronizing generation and consumption of isochronous data | — | 2003-09-23 |
| 6618782 | Computer interconnection bus link layer | Larry D. Hewitt, Alfred C. Hartmann, Geoffrey S. Strongin | 2003-09-09 |
| 6611891 | Computer resource configuration mechanism across a multi-pipe communication link | Larry D. Hewitt | 2003-08-26 |
| 6601178 | System power management partitioned across a serial bus | — | 2003-07-29 |
| 6557048 | Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof | James B. Keller, Derrick R. Meyer, Larry D. Hewitt | 2003-04-29 |
| 6532019 | Input/output integrated circuit hub incorporating a RAMDAC | Larry D. Hewitt | 2003-03-11 |
| 6502123 | Isochronous system using certified drivers to ensure system stability | — | 2002-12-31 |
| 6499079 | Subordinate bridge structure for a point-to-point computer interconnection bus | — | 2002-12-24 |
| 6470410 | Target side concentrator mechanism for connecting multiple logical pipes to a single function utilizing a computer interconnection bus | Geoffrey S. Strongin | 2002-10-22 |
| 6457084 | Target side distributor mechanism for connecting multiple functions to a single logical pipe of a computer interconnection bus | Geoffrey S. Strongin | 2002-09-24 |
| 6457081 | Packet protocol for reading an indeterminate number of data bytes across a computer interconnection bus | — | 2002-09-24 |
| 6421751 | Detecting a no-tags-free condition in a computer system having multiple outstanding transactions | — | 2002-07-16 |
| 6421702 | Interrupt driven isochronous task scheduler system | — | 2002-07-16 |
| 6418459 | Isochronous task scheduling structure for a non-real-time operating system | — | 2002-07-09 |
| 6404771 | Clock lead/lag extraction in an isochronous data bus | — | 2002-06-11 |
| 6389526 | Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system | James B. Keller, Larry D. Hewitt, Geoffrey S. Strongin | 2002-05-14 |
| 6385705 | Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system | James B. Keller, Larry D. Hewitt, Geoffrey S. Strongin | 2002-05-07 |
| 6336179 | Dynamic scheduling mechanism for an asynchronous/isochronous integrated circuit interconnect bus | — | 2002-01-01 |
| 6279058 | Master isochronous clock structure having a clock controller coupling to a CPU and two data buses | — | 2001-08-21 |
| 6272465 | Monolithic PC audio circuit | Larry D. Hewitt, Jeffrey M. Blumenthal, Geoffrey E. Brehmer, Glen W. Brown, Carlin D. Cabler +10 more | 2001-08-07 |
| 6263385 | PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus | David N. Suggs | 2001-07-17 |
| 6202164 | Data rate synchronization by frame rate adjustment | — | 2001-03-13 |
| 6199132 | Communication link with isochronous and asynchronous priority modes | Larry D. Hewitt | 2001-03-06 |