Issued Patents All Time
Showing 51–55 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6084679 | Universal alignment marks for semiconductor defect capture and analysis | Paul J. Steffan | 2000-07-04 |
| 6025259 | Dual damascene process using high selectivity boundary layers | Paul J. Steffan, Thomas C. Scholer | 2000-02-15 |
| 6025272 | Method of planarize and improve the effectiveness of the stop layer | Thomas C. Scholer, Paul J. Steffan | 2000-02-15 |
| 6013570 | LDD transistor using novel gate trim technique | Patrick K. Cheung, Paul J. Steffan | 2000-01-11 |
| 5985753 | Method to manufacture dual damascene using a phantom implant mask | Paul J. Steffan, Thomas C. Scholer | 1999-11-16 |