| 7139955 |
Hierarchically-controlled automatic test pattern generation |
John G. Rohrbaugh |
2006-11-21 |
| 7039845 |
Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults |
Manish Sharma |
2006-05-02 |
| 6944837 |
System and method for evaluating an integrated circuit design |
John G. Rohrbaugh, Christopher M. Juenemann |
2005-09-13 |
| 6895562 |
Partitioning integrated circuit hierarchy |
John G. Rohrbaugh, Daryl Allred |
2005-05-17 |
| 6865706 |
Apparatus and method for generating a set of test vectors using nonrandom filling |
John G. Rohrbaugh |
2005-03-08 |
| 6763486 |
Method and apparatus of boundary scan testing for AC-coupled differential data paths |
Benny Wing Hung Lai, Young Gon Kim, Kenneth P. Parker |
2004-07-13 |
| 6737858 |
Method and apparatus for testing current sinking/sourcing capability of a driver circuit |
Hugh Wallace |
2004-05-18 |
| 6721920 |
Systems and methods for facilitating testing of pad drivers of integrated circuits |
John G. Rohrbaugh, Shad Shepston |
2004-04-13 |
| 6715105 |
Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port |
— |
2004-03-30 |
| 6708139 |
Method and apparatus for measuring the quality of delay test patterns |
Manish Sharma |
2004-03-16 |
| 6707313 |
Systems and methods for testing integrated circuits |
John G. Rohrbaugh |
2004-03-16 |
| 6653957 |
SERDES cooperates with the boundary scan test technique |
Sylvia Patterson |
2003-11-25 |
| 6396312 |
Gate transition counter |
Shad Shepston, John G. Rohrbaugh |
2002-05-28 |
| 6380780 |
Integrated circuit with scan flip-flop |
Robert Campbell Aitken, Haluk Konuk, John Stephen Walther |
2002-04-30 |
| 6239607 |
Simulation-based method for estimating leakage currents in defect-free integrated circuits |
Peter C. Maxwell |
2001-05-29 |
| 5905986 |
Highly compressible representation of test pattern data |
John G. Rohrbaugh |
1999-05-18 |