Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7380189 | Circuit for PLL-based at-speed scan testing | — | 2008-05-27 |
| 7065693 | Implementation of test patterns in automated test equipment | — | 2006-06-20 |
| 6940766 | Row-column repair technique for semiconductor memory arrays | José L. Landivar, Zongbo Chen | 2005-09-06 |
| 6914459 | Clock multiplier using masked control of clock pulses | Vincent R. von Kaenel, Dai Le | 2005-07-05 |
| 6771549 | Row-column repair technique for semiconductor memory arrays | José L. Landivar, Zongbo Chen | 2004-08-03 |
| 6756827 | Clock multiplier using masked control of clock pulses | Vincent R. von Kaenel, Dai Le | 2004-06-29 |
| 6380780 | Integrated circuit with scan flip-flop | Robert Campbell Aitken, Jeff Rearick, John Stephen Walther | 2002-04-30 |
| 5963046 | Method for detecting and locating open-circuit defects within digital CMOS integrated circuits | — | 1999-10-05 |
| 5600787 | Method and data processing system for verifying circuit test vectors | Wilburn C. Underwood, Wai-on Law, Sungho Kang | 1997-02-04 |
| 5583787 | Method and data processing system for determining electrical circuit path delays | Wilburn C. Underwood, Sungho Kang, Wai-on Law | 1996-12-10 |
| 5517506 | Method and data processing system for testing circuits using boolean differences | Wilburn C. Underwood, Sungho Kang, Wai-on Law | 1996-05-14 |