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Circuit for PLL-based at-speed scan testing |
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2008-05-27 |
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2006-06-20 |
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Row-column repair technique for semiconductor memory arrays |
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Clock multiplier using masked control of clock pulses |
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Row-column repair technique for semiconductor memory arrays |
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Clock multiplier using masked control of clock pulses |
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Method for detecting and locating open-circuit defects within digital CMOS integrated circuits |
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1999-10-05 |
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