VS

Vladimir Sindalovsky

AS Agere Systems: 40 patents #7 of 1,849Top 1%
LS Lsi: 14 patents #60 of 1,740Top 4%
AT AT&T: 4 patents #4,399 of 18,772Top 25%
AP Avago Technologies General Ip (Singapore) Pte.: 3 patents #357 of 2,004Top 20%
AG Agere Systems Guardian: 2 patents #139 of 810Top 20%
📍 Perkasie, PA: #1 of 222 inventorsTop 1%
🗺 Pennsylvania: #423 of 74,527 inventorsTop 1%
Overall (All Time): #36,001 of 4,157,543Top 1%
63
Patents All Time

Issued Patents All Time

Showing 26–50 of 63 patents

Patent #TitleCo-InventorsDate
7848473 Phase interpolator having a phase jump Ronald L. Freyman, Lane A. Smith 2010-12-07
7792234 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system Pervez M. Aziz, Gregory W. Sheets 2010-09-07
7787515 Method and apparatus for generation of asynchronous clock for spread spectrum transmission Mohammad S. Mobin, Gregory W. Sheets, William B. Wilson, Craig B. Ziemer 2010-08-31
7778377 Methods and apparatus for spread spectrum generation using a voltage controlled delay loop Lane A. Smith, Craig B. Ziemer 2010-08-17
7773667 Pseudo asynchronous serializer deserializer (SERDES) testing Lane A. Smith, Ronald L. Freyman, Max J. Olsen 2010-08-10
7724857 Method and apparatus for improving linearity in clock and data recovery systems Christopher J. Abel, Joseph Anidjar, Craig B. Ziemer 2010-05-25
7711043 Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye Mohammad S. Mobin, Gary E. Schiessler, Gregory W. Sheets, Lane A. Smith 2010-05-04
7649933 Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization Christopher J. Abel, Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith 2010-01-19
7599461 Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern Pervez M. Aziz, Lane A. Smith 2009-10-06
7593498 Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications Xingdong Dai 2009-09-22
7561653 Method and apparatus for automatic clock alignment Lane A. Smith 2009-07-14
7549074 Content deskewing for multichannel synchronization Ravikumar Charath, Lane A. Smith 2009-06-16
7526033 Serializer deserializer (SERDES) testing Lane A. Smith 2009-04-28
7495494 Parallel trimming method and apparatus for a voltage controlled delay loop Ronald L. Freyman, Mohammad S. Mobin, Lane A. Smith 2009-02-24
7425856 Phase interpolator with output amplitude correction Christopher J. Abel, Joseph Anidjar, Craig B. Ziemer 2008-09-16
7421050 Parallel sampled multi-stage decimated digital loop filter for clock/data recovery Pervez M. Aziz, Donald R. Laturell 2008-09-02
7346879 Symmetric signal distribution through abutment connection Jung Ho Cho, Robert M. Kylor, Lane A. Smith 2008-03-18
7330060 Method and apparatus for sigma-delta delay control in a delay-locked-loop Christopher J. Abel, Abhishek Duggal, Peter C. Metz 2008-02-12
7312667 Statically controlled clock source generator for VCDL clock phase trimming Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Craig B. Ziemer 2007-12-25
7236037 Alternating clock signal generation for delay loops Christopher J. Abel, Craig B. Ziemer 2007-06-26
7212048 Multiple phase detection for delay loops Peter C. Metz, Lane A. Smith 2007-05-01
7190198 Voltage controlled delay loop with central interpolator Ronald L. Freyman, Lane A. Smith, Craig B. Ziemer 2007-03-13
7173459 Trimming method and apparatus for voltage controlled delay loop with central interpolator Ronald L. Freyman, Mohammad S. Mobin, Lane A. Smith 2007-02-06
7158592 Method and apparatus for synchronizing data transfer James Walter Hofmann, Jr., Donald R. Laturell, Steven E. Strauss, Eric Wilcox 2007-01-02
7003094 Adaptive interference cancellation for ADSL Jonathan H. Fischer, Donald R. Laturell 2006-02-21