Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Peter C. Metz — 15 Patents

ASAgere Systems: 8 patents #142 of 1,849Top 8%
Cisco: 5 patents #2,819 of 13,007Top 25%
ATAT&T: 2 patents #7,295 of 18,772Top 40%
Emmaus, PA: #35 of 365 inventorsTop 10%
Pennsylvania: #4,990 of 74,527 inventorsTop 7%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Peter C. Metz has been granted 15 US patents while listed as an inventor at Agere Systems. The first was granted in 1990 and the most recent in September 2024. Peter C. Metz ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Peter C. Metz in Emmaus, PA, US.

Patents per Year

Patents granted per year, 1990 to 2024Bar chart with a peak of 3 patents in 2007.peak 31990: 1 patents19901991: 1 patents19912004: 1 patents20042007: 3 patents20072008: 3 patents20082009: 1 patents20092015: 1 patents20152022: 2 patents20222024: 2 patents2024

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12095421 Tunable driver Craig S. Appel, Joseph V. Pampanin, Sanjay Sunder 2024-09-17 $82,028,000
11947239 Optical driver with active boost Craig S. Appel 2024-04-02 $74,581,000
11454856 Optical driver with active boost Craig S. Appel 2022-09-27 $102,864,000
11411538 Tunable driver Craig S. Appel, Joseph V. Pampanin, Sanjay Sunder 2022-08-09 $30,886,000
8929689 Optical modulator utilizing unary encoding and auxiliary modulator section for load balancing Bipin Dama, Kalpendu Shastri 2015-01-06 $57,563,000
7486746 Clock and data recovery with extended integration cycles Donald R. Laturell, Baiying Yu 2009-02-03
7400181 Method and apparatus for delay line control using receive data Gregory W. Sheets 2008-07-15
7352313 Method and apparatus for master/slave digital-to-analog conversion Christopher J. Abel 2008-04-01
7330060 Method and apparatus for sigma-delta delay control in a delay-locked-loop Christopher J. Abel, Abhishek Duggal, Vladimir Sindalovsky 2008-02-12
7271621 Method and apparatus for trimming a phase detector in a delay-locked-loop 2007-09-18
7212048 Multiple phase detection for delay loops Vladimir Sindalovsky, Lane A. Smith 2007-05-01
7209525 Clock and data recovery with extended integration cycles Donald R. Laturell, Baiying Yu 2007-04-24
6700944 Phase detector for clock and data recovery James D. Chlipala, John M. Khoury, Kadaba Lakshmikumar 2004-03-02
5040035 MOS devices having improved threshold match Thaddeus John Gabara 1991-08-13
4947061 CMOS to ECL output buffer circuit Robert L. Pritchett 1990-08-07