MM

Mohammad S. Mobin

AS Agere Systems: 51 patents #2 of 1,849Top 1%
LS Lsi: 23 patents #23 of 1,740Top 2%
AT AT&T: 15 patents #1,136 of 18,772Top 7%
AP Avago Technologies General Ip (Singapore) Pte.: 10 patents #61 of 2,004Top 4%
NV NVIDIA: 6 patents #1,173 of 7,811Top 20%
AG Agere Systems Guardian: 3 patents #85 of 810Top 15%
AI At & T Ipm: 2 patents #5 of 189Top 3%
AL Avago Technologies International Sales Pte. Limited: 2 patents #297 of 1,094Top 30%
📍 Orefield, PA: #1 of 99 inventorsTop 2%
🗺 Pennsylvania: #125 of 74,527 inventorsTop 1%
Overall (All Time): #11,499 of 4,157,543Top 1%
112
Patents All Time

Issued Patents All Time

Showing 76–100 of 112 patents

Patent #TitleCo-InventorsDate
7649933 Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization Christopher J. Abel, Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith 2010-01-19
7606302 Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel Gregory W. Sheets, Lane A. Smith, Paul H. Tracy 2009-10-20
7587640 Method and apparatus for monitoring and compensating for skew on a high speed parallel bus Gregory W. Sheets, Lane A. Smith 2009-09-08
7570708 Serdes auto calibration and load balancing Donald R. Laturell, Gregory W. Sheets, Lane A. Smith 2009-08-04
7495494 Parallel trimming method and apparatus for a voltage controlled delay loop Ronald L. Freyman, Vladimir Sindalovsky, Lane A. Smith 2009-02-24
7411531 Methods and apparatus for asynchronous sampling of a received signal at a downsampled rate Pervez M. Aziz 2008-08-12
7378906 Method and apparatus for performing digital pre-distortion Jeffrey H. Saunders, Lane A. Smith 2008-05-27
7312667 Statically controlled clock source generator for VCDL clock phase trimming Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith, Craig B. Ziemer 2007-12-25
7218557 Method and apparatus for adaptive determination of timing signals on a high speed parallel bus James D. Chlipala 2007-05-15
7193461 Method and apparatus for performing digital pre-distortion Jeffrey H. Saunders, Lane A. Smith 2007-03-20
7173459 Trimming method and apparatus for voltage controlled delay loop with central interpolator Ronald L. Freyman, Vladimir Sindalovsky, Lane A. Smith 2007-02-06
6826719 Cellular CDMA transmission system Himanshu M. Thaker, Charles A. Webb, III, Lesley Jen-Yuan Wu 2004-11-30
6791991 Channel sequencing using a round-robin scheduler Kalyan Mondal, Himanshu M. Thaker 2004-09-14
6675327 Communications system including lower rate parallel electronics with skew compensation and associated methods Michael S. Shaffer, Himanshu M. Thaker, Charles A. Webb, III, Lesley Jen-Yuan Wu 2004-01-06
6665825 Cellular CDMA transmission system Himanshu M. Thaker, Charles A. Webb, III, Lesley Jen-Yuan Wu 2003-12-16
6532273 Efficient polyphase decimation filter Marta M. Rambaud 2003-03-11
6522696 Adaptive frequency correction in a wireless communications system, such as for GSM and IS54 Kalyan Mondal 2003-02-18
6295325 Fixed clock based arbitrary symbol rate timing recovery loop Cecil W. Farrow, Daniel J. Udovic, Vahid Marandi, Kaylan Mondal, Kai-Chuen Wong 2001-09-25
6272188 Single-cycle accelerator for extremun state search Sivanand Simanapalli, Larry R. Tate 2001-08-07
6249554 Power based digital automatic gain control circuit Akkas T. Sufi 2001-06-19
6081565 Amplitude based coarse automatic gain control circuit Vahid Marandi, Kalyan Mondal, Akkas T. Sufi 2000-06-27
6009128 Metric acceleration on dual MAC processor Sivanand Simanapalli, Larry R. Tate 1999-12-28
5872801 Method of compensating for doppler error in a wireless communications system, such as for GSM and IS54 1999-02-16
5748680 Coarse frequency burst detector for a wireline communications system 1998-05-05
5748682 Oscillator frequency offset error estimator for communications systems 1998-05-05