Daniel Pugh — 23 Patents at Achronix Semiconductor

Daniel Pugh has been granted 23 US patents while listed as an inventor at Achronix Semiconductor. The first was granted in 2004 and the most recent in November 2024. Daniel Pugh ranks #178,160 of 4,157,543 US inventors in our database (top 4.3%). Patent records list Daniel Pugh in San Jose, CA, US.

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Showing 1–23 of 23 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12141088	Cascade communications between FPGA tiles	Raymond Nijssen, Michael Fitton, Marcel Van der Goot	2024-11-12
12034446	Fused memory and arithmetic circuit	Raymond Nijssen, Michael Fitton	2024-07-09
12014150	Multiple mode arithmetic circuit	Raymond Nijssen, Michael Fitton, Marcel Van der Goot	2024-06-18
11734216	Cascade communications between FPGA tiles	Raymond Nijssen, Michael Fitton, Marcel Van der Goot	2023-08-22
11650792	Multiple mode arithmetic circuit	Raymond Nijssen, Michael Fitton, Marcel Van der Goot	2023-05-16
11288220	Cascade communications between FPGA tiles	Raymond Nijssen, Michael Fitton, Marcel Van der Goot	2022-03-29
11256476	Multiple mode arithmetic circuit	Raymond Nijssen, Michael Fitton, Marcel Van der Goot	2022-02-22
10963221	Efficient FPGA multipliers	Raymond Nijssen	2021-03-30
10790830	Fused memory and arithmetic circuit	Raymond Nijssen, Michael Fitton	2020-09-29
10656915	Efficient FPGA multipliers	Raymond Nijssen	2020-05-19
8463836	Performing mathematical and logical operations in multiple sub-cycles	Jason Redgrave, Andrew Caldwell	2013-06-11
8434045	System and method of providing a memory hierarchy	Herman Schmit, Steven Teig	2013-04-30
7971172	IC that efficiently replicates a function to save logic and routing resources	Andrew Caldwell	2011-06-28
7930666	System and method of providing a memory hierarchy	Herman Schmit, Steven Teig	2011-04-19
7818361	Method and apparatus for performing two's complement multiplication	—	2010-10-19
7765249	Use of hybrid interconnect/logic circuits for multiplication	Herman Schmit, Jason Redgrave, Andrew Caldwell	2010-07-27
7587697	System and method of mapping memory blocks in a configurable integrated circuit	Herman Schmit, Steven Teig	2009-09-08
7372297	Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources	Andrew Caldwell	2008-05-13
7080107	Gold code generator design	Mark Edward Rollins	2006-07-18	$11,508,000
7009421	Field programmable gate array core cell with efficient logic packing	Andrew W. Fox, Dale Wong	2006-03-07
6904105	Method and implemention of a traceback-free parallel viterbi decoder	—	2005-06-07	$27,808,000
6834291	Gold code generator design	Mark Edward Rollins	2004-12-21	$44,553,000
6801052	Field programmable gate array core cell with efficient logic packing	Andrew W. Fox, Dale Wong	2004-10-05

Daniel Pugh — 23 Patents

Patents per Year

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