Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and implemention of a traceback-free parallel viterbi decoder

Method and implemention of a traceback-free parallel viterbi decoder

US Patent 6904105 · Granted Jun 7, 2005

Estimated economic value: $27,808,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Cascade communications between FPGA tiles2024
Fused memory and arithmetic circuit2024
Multiple mode arithmetic circuit2024
Cascade communications between FPGA tiles2023
Multiple mode arithmetic circuit2023
Cascade communications between FPGA tiles2022
Multiple mode arithmetic circuit2022
Efficient FPGA multipliers2021
Fused memory and arithmetic circuit2020
Efficient FPGA multipliers2020
Performing mathematical and logical operations in multiple sub-cycles2013
System and method of providing a memory hierarchy2013