Issued Patents 2025
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12223165 | Multicore, multibank, fully concurrent coherence controller | Matthew D. Pierson, Kai Chirca | 2025-02-11 |
| 12223327 | CPUs with capture queues to save and restore intermediate results and out-of-order results | Duc Quang Bui, Joseph Zbiciak, Reid E. Tatge | 2025-02-11 |
| 12217054 | Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof | Duc Quang Bui, Alan L. Davis, Dheera Balasubramanian Samudrala | 2025-02-04 |
| 12216591 | Atomic compare and swap in a coherent cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2025-02-04 |
| 12210463 | Aggressive write flush scheme for a victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-28 |
| 12204905 | Inserting predefined pad values into a stream of vectors | Asheesh Bhardwaj, Son Hung Tran | 2025-01-21 |
| 12197917 | Exit history based branch prediction | Kai Chirca, David E. Smith, Paul Daniel Gauvreau | 2025-01-14 |
| 12197347 | Methods and apparatus to reduce bank pressure using aggressive write merging | Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-14 |
| 12197332 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson | 2025-01-14 |
| 12189540 | Fully pipelined read-modify-write support | Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-07 |