| 12386623 |
Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor |
Timothy David Anderson, Joseph Zbiciak |
2025-08-12 |
| 12373242 |
Entering protected pipeline mode without annulling pending instructions |
Timothy David Anderson |
2025-07-29 |
| 12366906 |
Controlling the number of powered vector lanes via a register field |
Timothy David Anderson |
2025-07-22 |
| 12341534 |
Butterfly network on load data return |
Dheera Balasubramanian, Joseph Zbiciak, Timothy David Anderson |
2025-06-24 |
| 12321750 |
Entering protected pipeline mode with clearing |
Timothy David Anderson, Joseph Zbiciak, Mel Alan Phipps, Todd T. Hahn |
2025-06-03 |
| 12321749 |
Look up table with data element promotion |
Dheera Balasubramanian, Naveen Bhoria, Sahithi KRISHNA |
2025-06-03 |
| 12314720 |
Look-up table write |
Naveen Bhoria, Dheera Balasubramanian Samudrala |
2025-05-27 |
| 12307251 |
Vector reverse |
Timothy David Anderson |
2025-05-20 |
| 12265827 |
Forming constant extensions in the same execute packet in a VLIW processor |
Timothy David Anderson, Joseph Zbiciak |
2025-04-01 |
| 12260219 |
Multiple instruction set architectures on a processing device |
Timothy David Anderson, Paul Daniel Gauvreau |
2025-03-25 |
| 12242852 |
Look-up table initialize |
Naveen Bhoria, Dheera Balasubramanian Samudrala, Rama Venkatasubramanian |
2025-03-04 |
| 12223327 |
CPUs with capture queues to save and restore intermediate results and out-of-order results |
Timothy David Anderson, Joseph Zbiciak, Reid E. Tatge |
2025-02-11 |
| 12217054 |
Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof |
Alan L. Davis, Dheera Balasubramanian Samudrala, Timothy David Anderson |
2025-02-04 |