| 12430201 |
Multi-processor bridge with cache allocate awareness |
Daniel Wu, Matthew D. Pierson |
2025-09-30 |
| 12423481 |
Secure master and secure guest endpoint security firewall |
Timothy David Anderson, Joseph Zbiciak, Matthew D. Pierson |
2025-09-23 |
| 12386696 |
Delayed snoop for improved multi-process false sharing parallel thread performance |
Timothy David Anderson |
2025-08-12 |
| 12379929 |
Branch prediction using loop iteration count |
Paul Daniel Gauvreau, David E. Smith |
2025-08-05 |
| 12373515 |
Computational primitives using a matrix multiplication accelerator |
Arthur John Redfern, Timothy David Anderson, Chenchi Luo, Zhenhua Yu |
2025-07-29 |
| 12360844 |
Credit aware central arbitration for multi-endpoint, multi-core system |
Matthew D. Pierson, Daniel Wu |
2025-07-15 |
| 12360843 |
Multicore shared cache operation engine |
Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew D. Pierson |
2025-07-15 |
| 12333284 |
Nested loop control |
Timothy David Anderson, Todd T. Hahn, Alan L. Davis |
2025-06-17 |
| 12321282 |
Slot/sub-slot prefetch architecture for multiple memory requestors |
Joseph Zbiciak, Matthew D. Pierson |
2025-06-03 |
| 12314187 |
Software-hardware memory management modes |
Timothy David Anderson, Joseph Zbiciak, Daniel Wu |
2025-05-27 |
| 12223165 |
Multicore, multibank, fully concurrent coherence controller |
Matthew D. Pierson, Timothy David Anderson |
2025-02-11 |
| 12197332 |
Memory pipeline control in a hierarchical memory system |
Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson |
2025-01-14 |
| 12197917 |
Exit history based branch prediction |
Timothy David Anderson, David E. Smith, Paul Daniel Gauvreau |
2025-01-14 |