Issued Patents 2025
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373286 | Handling non-correctable errors | David Matthew Thompson | 2025-07-29 |
| 12332790 | Multi-level cache security | David Matthew Thompson, Naveen Bhoria | 2025-06-17 |
| 12321277 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2025-06-03 |
| 12321270 | Hardware coherence for memory controller | David Matthew Thompson, Naveen Bhoria | 2025-06-03 |
| 12271314 | Cache size change | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2025-04-08 |
| 12197331 | Hardware coherence signaling protocol | David Matthew Thompson, Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-14 |
| 12197332 | Memory pipeline control in a hierarchical memory system | Timothy David Anderson, Kai Chirca, David Matthew Thompson | 2025-01-14 |