Issued Patents 2025
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431197 | Programming operation using cache register release in a memory sub-system | Walter Di Francesco, Umberto Siciliani | 2025-09-30 |
| 12423002 | Selectively programming retired wordlines of a memory device | Kishore Kumar Muchherla, Akira Goda, Jeffrey S. McNeil, Niccolo' Righetti, Silvia Beltrami +1 more | 2025-09-23 |
| 12411770 | Hybrid parallel programming of single-level cell memory | Umberto Siciliani, Walter Di Francesco | 2025-09-09 |
| 12373109 | Validating read level voltage in memory devices | Jeffrey S. McNeil, Eric N. Lee, Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Kishore Kumar Muchherla +1 more | 2025-07-29 |
| 12340851 | Memories for performing successive programming operations | Umberto Siciliani, Walter Di Francesco, Dheeraj Srinivasan | 2025-06-24 |
| 12334142 | Sacrificial strings in a memory device to detect read disturb | Kishore Kumar Muchherla, Akira Goda, Jeffrey S. McNeil, Eric N. Lee | 2025-06-17 |
| 12327595 | Shortened single-level cell memory programming | Leo Raimondo, Federica Paolini, Umberto Siciliani, Gianfranco Valeri, Davide Esposito +1 more | 2025-06-10 |
| 12322440 | Programming operation of memory device being switched from high-density mode to high speed mode and/or lower power mode | Andrea Smaniotto | 2025-06-03 |
| 12315573 | Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device | Mattia Cichocki, Tommaso Vali, Guido Luciano Rizzo, Chang Wan Ha, Richard Fastow | 2025-05-27 |
| 12315574 | Auto-calibrated corrective read | Chengbin Sun, Carmine Miccoli, Srinath Venkatesan, Walter Di Francesco | 2025-05-27 |
| 12315575 | Boost voltage modulated corrective read | Nagendra Prasad Ganesh Rao, Dheeraj Srinivasan, Paing Z. Htet, Sead Zildzic | 2025-05-27 |
| 12265447 | Memory sub-system with dynamic calibration using component-based function(s) | Gerald L. Cadloni, Bruce A. Liikanen | 2025-04-01 |
| 12217799 | Parallelized defect detection across multiple sub-blocks in a memory device | Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao +2 more | 2025-02-04 |
| 12205653 | Wordline or pillar state detection for faster read access times | Shyam Sunder Raghunathan, Walter Di Francesco | 2025-01-21 |