Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423002 | Selectively programming retired wordlines of a memory device | Kishore Kumar Muchherla, Akira Goda, Niccolo' Righetti, Silvia Beltrami, Violante Moschiano +1 more | 2025-09-23 |
| 12373109 | Validating read level voltage in memory devices | Eric N. Lee, Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Patrick R. Khayat +1 more | 2025-07-29 |
| 12347485 | Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device | Sheyang Ning, Lawrence Celso Miranda, Tomoko Ogura Iwasaki | 2025-07-01 |
| 12340126 | Workload-based scan optimization | Kishore Kumar Muchherla, Eric N. Lee, Jonathan S. Parry, Lakshmi Kalpana Vakati | 2025-06-24 |
| 12334142 | Sacrificial strings in a memory device to detect read disturb | Kishore Kumar Muchherla, Violante Moschiano, Akira Goda, Eric N. Lee | 2025-06-17 |
| 12327048 | Using duplicate data for improving error correction capability | Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Patrick R. Khayat, Sundararajan Sankaranarayanan, Jeremy Binfet +1 more | 2025-06-10 |
| 12224012 | All level coarse/fine programming of memory cells | Lawrence Celso Miranda, Tomoko Ogura Iwasaki, Sheyang Ning | 2025-02-11 |
| 12217799 | Parallelized defect detection across multiple sub-blocks in a memory device | Paing Z. Htet, Akira Goda, Eric N. Lee, Junwyn A. Lacsao, Kishore Kumar Muchherla +2 more | 2025-02-04 |
| 12211552 | Concurrent slow-fast memory cell programming | Lawrence Celso Miranda, Tomoko Ogura Iwasaki, Sheyang Ning | 2025-01-28 |