Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406731 | Dynamic latches above a three-dimensional non-volatile memory array | Jiewei Chen, Mithun Kumar Ramasahayam, June Lee, Luyen Vu | 2025-09-02 |
| 12387790 | Double single level cell program in a memory device | Eric N. Lee, June Lee | 2025-08-12 |
| 12347485 | Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device | Sheyang Ning, Lawrence Celso Miranda, Jeffrey S. McNeil | 2025-07-01 |
| 12334163 | Single-level cell program-verify, latch-limited data recovery | Eric N. Lee | 2025-06-17 |
| 12272421 | Creating dynamic latches above a three-dimensional non-volatile memory array | Jiewei Chen, Mithun Kumar Ramasahayam | 2025-04-08 |
| 12254927 | In-line programming adjustment of a memory cell in a memory sub-system | Sheyang Ning, Lawrence Celso Miranda, Zhengyi Zhang | 2025-03-18 |
| 12224012 | All level coarse/fine programming of memory cells | Lawrence Celso Miranda, Sheyang Ning, Jeffrey S. McNeil | 2025-02-11 |
| 12211552 | Concurrent slow-fast memory cell programming | Lawrence Celso Miranda, Sheyang Ning, Jeffrey S. McNeil | 2025-01-28 |
| 12211548 | Erase operation with electron injection for reduction of cell-to-cell interference in a memory sub-system | Hong-Yan Chen, Priya Vemparala Guruswamy, Pamela Castalino | 2025-01-28 |