Issued Patents 2025
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431197 | Programming operation using cache register release in a memory sub-system | Violante Moschiano, Umberto Siciliani | 2025-09-30 |
| 12411770 | Hybrid parallel programming of single-level cell memory | Umberto Siciliani, Violante Moschiano | 2025-09-09 |
| 12393249 | Peak power management with data window reservation | Luca Nubile, Luigi Pilolli | 2025-08-19 |
| 12393526 | NAND page buffer based security operations | Jeremy Binfet, Lance W. Dover, Tommaso Vali | 2025-08-19 |
| 12340851 | Memories for performing successive programming operations | Umberto Siciliani, Violante Moschiano, Dheeraj Srinivasan | 2025-06-24 |
| 12327595 | Shortened single-level cell memory programming | Leo Raimondo, Federica Paolini, Umberto Siciliani, Violante Moschiano, Gianfranco Valeri +1 more | 2025-06-10 |
| 12315574 | Auto-calibrated corrective read | Chengbin Sun, Carmine Miccoli, Violante Moschiano, Srinath Venkatesan | 2025-05-27 |
| 12282669 | Prioritized power budget arbitration for multiple concurrent memory access operations | Luca Nubile, Fumin Gu, Ali Mohammadzadeh, Biagio Iorio, Liang Yu | 2025-04-22 |
| 12205653 | Wordline or pillar state detection for faster read access times | Violante Moschiano, Shyam Sunder Raghunathan | 2025-01-21 |
| 12189949 | Bit error management in memory devices | Jeremy Binfet, Tommaso Vali, Luigi Pilolli, Angelo Covello, Andrea D'Alessandro +3 more | 2025-01-07 |