Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430136 | Systems and methods for branch misprediction aware cache prefetcher training | Gabriel H. Loh, John Kalamatianos | 2025-09-30 |
| 12387767 | Method and apparatus for quantization and dequantization of neural network input and output data using processing-in-memory | Ioannis Papadopoulos, Vignesh Adhinarayanan, Ashwin Aji | 2025-08-12 |
| 12373207 | Implementing a micro-operation cache with compaction | John Kalamatianos | 2025-07-29 |
| 12339783 | Managing a cache using per memory region reuse distance estimation | John Kalamatianos, Asmita Pal | 2025-06-24 |
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | John Kalamatianos, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan, Patrick J. Shyvers +1 more | 2025-05-20 |
| 12287739 | Accessing a cache based on an address translation buffer result | John Kalamatianos | 2025-04-29 |
| 12265470 | Bypassing cache directory lookups for processing-in-memory instructions | Travis Henry Boraten, David Andrew Werner | 2025-04-01 |
| 12197378 | Method and apparatus to expedite system services using processing-in-memory (PIM) | Kishore Punniyamurthy | 2025-01-14 |
| 12189953 | Speculative dram request enabling and disabling | John Kalamatianos | 2025-01-07 |