Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393518 | Deterministic mixed latency cache | — | 2025-08-19 |
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Jagadish B. Kotra, John Kalamatianos, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan +1 more | 2025-05-20 |
| 12266585 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2025-04-01 |