Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Jagadish B. Kotra, John Kalamatianos, Nicholas Dean Lance, Sriram Srinivasan, Patrick J. Shyvers +1 more | 2025-05-20 |
| 12282428 | Selective speculative prefetch requests for a last-level cache | Tarun Nakra, Akhil Arunkumar, Jay Fleischman | 2025-04-22 |
| 12204454 | System probe aware last level cache insertion bypassing | Jay Fleischman | 2025-01-21 |
| 12189530 | Suppressing cache line modification | — | 2025-01-07 |