Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Jagadish B. Kotra, John Kalamatianos, Paul James Moyer, Sriram Srinivasan, Patrick J. Shyvers +1 more | 2025-05-20 |