Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430136 | Systems and methods for branch misprediction aware cache prefetcher training | Jagadish B. Kotra, Gabriel H. Loh | 2025-09-30 |
| 12373207 | Implementing a micro-operation cache with compaction | Jagadish B. Kotra | 2025-07-29 |
| 12360907 | Region pattern-matching hardware prefetcher | Gabriel H. Loh, Marko Scrbak, Akhil Arunkumar | 2025-07-15 |
| 12339783 | Managing a cache using per memory region reuse distance estimation | Jagadish B. Kotra, Asmita Pal | 2025-06-24 |
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Jagadish B. Kotra, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan, Patrick J. Shyvers +1 more | 2025-05-20 |
| 12287739 | Accessing a cache based on an address translation buffer result | Jagadish B. Kotra | 2025-04-29 |
| 12189953 | Speculative dram request enabling and disabling | Jagadish B. Kotra | 2025-01-07 |