Issued Patents 2024
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148752 | High voltage transistor structures | Meng-Han Lin, Yong-Shiuan Tsair | 2024-11-19 |
| 12136627 | 3DIC structure for high voltage device on a SOI substrate | Harry-Hak-Lay Chuang, Hsin Fu Lin, Wei-Cheng Wu | 2024-11-05 |
| 12107001 | Semiconductor feature and method for manufacturing the same | Harry-Hak-Lay Chuang, Chung-Jen Huang, Wei-Cheng Wu | 2024-10-01 |
| 12101931 | Strap-cell architecture for embedded memory | Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair +2 more | 2024-09-24 |
| 12068032 | Device-region layout for embedded flash | Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu +2 more | 2024-08-20 |
| 12009033 | ONON sidewall structure for memory device and method for making the same | Chen-Ming Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin +5 more | 2024-06-11 |
| 11968828 | Method of forming a semiconductor device with a dual gate dielectric layer having middle portion thinner than the edge portions | Meng-Han Lin, Yong-Shiuan Tsair | 2024-04-23 |
| 11961826 | Bonded wafer device structure and methods for making the same | Harry-Hak-Lay Chuang, Wei-Cheng Wu | 2024-04-16 |
| 11942475 | High voltage transistor structure | Meng-Han Lin, Yong-Shiuan Tsair | 2024-03-26 |
| 11869888 | Polysilicon resistor structures | Meng-Han Lin, Yong-Shiuan Tsair | 2024-01-09 |
| 11869951 | Control gate strap layout to improve a word line etch process window | Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yong-Shiuan Tsair +2 more | 2024-01-09 |