Issued Patents 2024
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170117 | 3D NAND memory with built-in capacitor | Ching-Huang Lu, Zhenming Zhou | 2024-12-17 |
| 12154635 | Memory programming techniques to reduce power consumption | Henry Chin, Erika Penzo | 2024-11-26 |
| 12148480 | 3D NAND memory with fast corrective read | Jun Wan, Zhenming Zhou | 2024-11-19 |
| 12142326 | Adaptive programming delay scheme in a memory sub-system | Zhenming Zhou | 2024-11-12 |
| 12106812 | Detecting a memory write reliability risk without using a write verify operation | Zhenming Zhou, Tomer Eliash | 2024-10-01 |
| 12079079 | Proximity based parity data management | Zhenming Zhou, Wei Wang | 2024-09-03 |
| 12073905 | Adaptive error avoidance in the memory devices | Li-Te Chang, Murong Lang, Zhenming Zhou, Michael G. Miller | 2024-08-27 |
| 12067255 | Error detection for programming single level cells | Tomer Eliash | 2024-08-20 |
| 12057157 | Low power mode with read sequence adjustment | Jiahui Yuan, Kai Kirk | 2024-08-06 |
| 12057167 | Padding in flash memory blocks | Zhenming Zhou, Murong Lang | 2024-08-06 |
| 12027210 | Programming delay scheme for a memory sub-system based on memory reliability | Zhenming Zhou | 2024-07-02 |
| 12014049 | Adaptive sensing time for memory operations | Zhenming Zhou, Murong Lang, Ching-Huang Lu | 2024-06-18 |
| 11972809 | Selective inhibit bitline voltage to cells with worse program disturb | Sujjatul Islam, Ravi Kumar, Xue Bai Pitner | 2024-04-30 |
| 11972803 | Word line zone dependent pre-charge voltage | Fanqi Wu, Jiahui Yuan | 2024-04-30 |
| 11972814 | Verify techniques for current reduction in a memory device | Xue Bai Pitner, Ravi Kumar, Jiahui Yuan, Bo Lei, Zhenni Wan | 2024-04-30 |
| 11972801 | Program voltage dependent program source levels | Xue Bai Pitner, Sarath Puthenthermadam, Sujjatul Islam | 2024-04-30 |
| 11972122 | Memory read operation using a voltage pattern based on a read command type | Ching-Huang Lu, Zhenming Zhou | 2024-04-30 |
| 11894081 | EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures | Xue Bai Pitner, Ken Oowada | 2024-02-06 |
| 11887670 | Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption | Deepanshu Dutta, Jiahui Yuan | 2024-01-30 |
| 11875842 | Systems and methods for staggering read operation of sub-blocks | Deepanshu Dutta, Tai-Yuan Tseng | 2024-01-16 |