Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12112800 | High speed multi-level cell (MLC) programming in non-volatile memory structures | Xiang Yang, Muhammad Masuduzzaman, Jiacen Guo | 2024-10-08 |
| 12057175 | Memory apparatus and method of operation using state dependent strobe tier scan to reduce peak ICC | Chin-Yi Chen, Muhammad Masuduzzaman, Kou Tei, Hiroyuki Mizukoshi, Jiahui Yuan +1 more | 2024-08-06 |
| 12057168 | Neighbor aware multi-bias programming in scaled BICS | Muhammad Masuduzzaman | 2024-08-06 |
| 12051467 | Programming of memory cells using a memory string dependent program voltage | Huai-Yuan Tseng, Henry Chin | 2024-07-30 |
| 12051468 | Soft erase process during programming of non-volatile memory | Jiahui Yuan | 2024-07-30 |
| 12046302 | Edge word line concurrent programming with verify for memory apparatus with on-pitch semi-circle drain side select gate technology | Xiang Yang, Ken Oowada | 2024-07-23 |
| 11972812 | Non-volatile memory with data refresh based on data states of adjacent memory cells | Yi Song, Jiahui Yuan, Jun Wan | 2024-04-30 |
| 11961563 | Balancing peak power with programming speed in non-volatile memory | Towhidur Razzak, Jiahui Yuan | 2024-04-16 |
| 11894062 | Semi-circle drain side select gate maintenance by selective semi-circle dummy word line program | Xiang Yang, Gerrit Jan Hemink, Shubhajit Mukherjee | 2024-02-06 |
| 11887677 | Quick pass write programming techniques in a memory device | Muhammad Masuduzzaman, Gerrit Jan Hemink | 2024-01-30 |
| 11887670 | Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption | Yu-Chung Lien, Jiahui Yuan | 2024-01-30 |
| 11875842 | Systems and methods for staggering read operation of sub-blocks | Yu-Chung Lien, Tai-Yuan Tseng | 2024-01-16 |