Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170117 | 3D NAND memory with built-in capacitor | Yu-Chung Lien, Zhenming Zhou | 2024-12-17 |
| 12131783 | Early discharge sequences during read recovery to alleviate latent read disturb | Xiangyu Yang | 2024-10-29 |
| 12124705 | Memory operation based on block-associated temperature | Pitamber Shukla, Devin M. Batutis | 2024-10-22 |
| 12068036 | Adaptive erase pulse width modulation based on erase suspend during erase pulse ramping period | Jiun-Horng Lai, Pitamber Shukla, Chengkuan Yin, Yoshiaki Fukuzumi | 2024-08-20 |
| 12026394 | Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system | Zhenming Zhou, Murong Lang | 2024-07-02 |
| 12014050 | Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system | Zhenming Zhou, Murong Lang | 2024-06-18 |
| 12014049 | Adaptive sensing time for memory operations | Yu-Chung Lien, Zhenming Zhou, Murong Lang | 2024-06-18 |
| 11972122 | Memory read operation using a voltage pattern based on a read command type | Yu-Chung Lien, Zhenming Zhou | 2024-04-30 |
| 11967387 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Vinh Diep, Zhengyi Zhang, Yingda Dong | 2024-04-23 |
| 11947831 | Adaptive enhanced corrective read based on write and read temperature | Zhenming Zhou, Murong Lang, Nagendra Prasad Ganesh Rao | 2024-04-02 |
| 11901010 | Enhanced gradient seeding scheme during a program operation in a memory sub-system | Vinh Diep, Yingda Dong | 2024-02-13 |
| 11894069 | Unselected sub-block source line and bit line pre-charging to reduce read disturb | Xiangyu Yang, Hong-Yan Chen | 2024-02-06 |