Issued Patents 2024
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12142333 | Error correction in a memory device having an error correction code of a predetermined code rate | Kishore Kumar Muchherla | 2024-11-12 |
| 12119062 | Managing compensation for cell-to-cell coupling and lateral migration in memory devices based on a sensitivity metric | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-10-15 |
| 12099725 | Code rate as function of logical saturation | Kishore Kumar Muchherla, Jonathan S. Parry, Sivagnanam Parthasarathy, Akira Goda | 2024-09-24 |
| 12087374 | Managing compensation for cell-to-cell coupling and lateral migration in memory devices using segmentation | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-09-10 |
| 12086028 | Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate | Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Akira Goda | 2024-09-10 |
| 12057185 | Voltage calibration scans to reduce memory device overhead | Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley, Devin M. Batutis +4 more | 2024-08-06 |
| 12046307 | Managing program verify voltage offsets for charge coupling and lateral migration compensation in memory devices | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-07-23 |
| 12046298 | Managing compensation for charge coupling and lateral migration in memory devices | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-07-23 |
| 12032444 | Error correction with syndrome computation in a memory device | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-07-09 |
| 12014071 | Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism | Eyal En Gad, Sivagnanam Parthasarathy, Yoav Weinberg | 2024-06-18 |
| 11996860 | Scaled bit flip thresholds across columns for irregular low density parity check decoding | Eyal En Gad, Sivagnanam Parthasarathy, Yoav Weinberg | 2024-05-28 |
| 11994947 | Multi-layer code rate architecture for special event protection with reduced performance penalty | Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Sivagnanam Parthasarathy, Jonathan S. Parry | 2024-05-28 |
| 11983067 | Adjustment of code rate as function of memory endurance state metric | Kishore Kumar Muchherla, Niccolo′ Righetti, Sivagnanam Parthasarathy, Mark A. Helm, James Fitzpatrick +1 more | 2024-05-14 |
| 11966616 | Voltage bin calibration based on a voltage distribution reference voltage | Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2024-04-23 |
| 11934266 | Memory compaction management in memory devices | Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Patrick R. Khayat, Sampath K. Ratnam, Kishore Kumar Muchherla +2 more | 2024-03-19 |
| 11928347 | Managing voltage bin selection for blocks of a memory device | Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy +2 more | 2024-03-12 |
| 11923868 | Stall mitigation in iterative decoders | Sivagnanam Parthasarathy | 2024-03-05 |
| 11923867 | Iterative decoder with a dynamic maximum stop condition | Sivagnanam Parthasarathy | 2024-03-05 |
| 11915776 | Error avoidance based on voltage distribution parameters of block families | Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell, Larry J. Koudele | 2024-02-27 |
| 11901911 | Stall detection and mitigation in iterative decoders | Sivagnanam Parthasarathy | 2024-02-13 |
| 11886718 | Descrambling of scrambled linear codewords using non-linear scramblers | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-01-30 |
| 11886726 | Block family-based error avoidance for memory devices | Michael Sheperek, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley +3 more | 2024-01-30 |
| 11886336 | Managing workload of programming sets of pages to memory device | Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo | 2024-01-30 |
| 11869605 | Adjusting pass-through voltage based on threshold voltage shift | Kishore Kumar Muchherla, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy | 2024-01-09 |
| 11868639 | Providing recovered data to a new memory cell at a memory sub-system based on an unsuccessful error correction operation | Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell +2 more | 2024-01-09 |