Issued Patents 2024
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12105967 | Two-tier defect scan management | Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Jonathan S. Parry +1 more | 2024-10-01 |
| 12079517 | Buffer allocation for reducing block transit penalty | Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda +3 more | 2024-09-03 |
| 12051479 | Memory block programming using defectivity information | Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Jiangli Zhu, Peter Feeley +3 more | 2024-07-30 |
| 12001721 | Multiple-pass programming of memory cells using temporary parity generation | Kishore Kumar Muchherla, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare +3 more | 2024-06-04 |
| 11977778 | Workload-based scan optimization | Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry | 2024-05-07 |
| 11907066 | Managing storage of multiple plane parity data in a memory sub-system | Xiangang Luo, Jianmin Huang, Harish Reddy Singidi | 2024-02-20 |