Issued Patents 2024
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182318 | Cryptographic key management | Juane Li, Ying Yu Tai | 2024-12-31 |
| 12176060 | Open translation unit management using an adaptive read threshold | Murong Lang, Zhenming Zhou, Jian Huang, Zhongguang Xu | 2024-12-24 |
| 12165709 | Memory cell voltage level selection | Tingjun Xie, Murong Lang, Fangfang Zhu, Zhenming Zhou | 2024-12-10 |
| 12164811 | Concurrent command limiter for a memory system | Jason Duong, Fangfang Zhu, Juane Li, Chih-Kuo Kao | 2024-12-10 |
| 12147708 | Write determination counter | Seungjune Jeon | 2024-11-19 |
| 12148495 | Detect whether die or channel is defective to confirm temperature data | Venkata Naga Lakshman Pasala, Wei Wang | 2024-11-19 |
| 12093564 | Partition command queues for a memory device | Juane Li, Jason Duong, Fangfang Zhu, Chih-Kuo Kao | 2024-09-17 |
| 12086062 | Managing power loss in a memory device | Huapeng Guan, Frederick Adi, Yipei Yu, Venkata Naga Lakshman Pasala, Wei Wang | 2024-09-10 |
| 12079517 | Buffer allocation for reducing block transit penalty | Kishore Kumar Muchherla, Peter Feeley, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati +3 more | 2024-09-03 |
| 12050808 | Selecting a write operation mode from multiple write operation modes | Zhenlei Shen, Fangfang Zhu, Tingjun Xie | 2024-07-30 |
| 12051479 | Memory block programming using defectivity information | Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Peter Feeley +3 more | 2024-07-30 |
| 12039196 | Double threshold controlled scheduling of memory access commands | Wei Wang, Ying Yu Tai, Jason Duong, Chih-Kuo Kao | 2024-07-16 |
| 12019915 | Hardware based status collector acceleration engine for memory sub-system operations | Fangfang Zhu, Ying Yu Tai, Wei Wang | 2024-06-25 |
| 12001721 | Multiple-pass programming of memory cells using temporary parity generation | Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao +3 more | 2024-06-04 |
| 11971772 | Unified sequencer concurrency controller for a memory sub-system | Fangfang Zhu, Ying Yu Tai | 2024-04-30 |
| 11966591 | Apparatus with read level management and methods for operating the same | Murong Lang, Tingjun Xie, Fangfang Zhu, Zhenming Zhou | 2024-04-23 |
| 11947421 | Decreasing a quantity of queues to adjust a read throughput level for a data recovery operation | Zhenming Zhou, Jian Huang | 2024-04-02 |
| 11923001 | Managing the programming of an open translation unit | Murong Lang, Zhenming Zhou, Jian Huang, Tingjun Xie, Nagendra Prasad Ganesh Rao +1 more | 2024-03-05 |
| 11914889 | Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system | Murong Lang, Tingjun Xie, Wei Wang, Frederick Adi, Zhenming Zhou | 2024-02-27 |
| 11907563 | Clock domain crossing queue | Yueh-Hung Chen, Chih-Kuo Kao, Ying Yu Tai | 2024-02-20 |
| 11899972 | Reduce read command latency in partition command scheduling at a memory device | Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao | 2024-02-13 |
| 11893280 | Concurrent command limiter for a memory system | Jason Duong, Fangfang Zhu, Juane Li, Chih-Kuo Kao | 2024-02-06 |
| 11881284 | Open translation unit management using an adaptive read threshold | Murong Lang, Zhenming Zhou, Jian Huang, Zhongguang Xu | 2024-01-23 |
| 11880600 | Consolidating write request in cache memory | Ning Chen, Yi-Min Lin, Fangfang Zhu | 2024-01-23 |
| 11874779 | Scheduling of read operations and write operations based on a data bus mode | Wei Wang, Ying Yu Tai, Samir Mittal | 2024-01-16 |