Issued Patents 2024
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12131060 | Quick charge loss mitigation using two-pass controlled delay | Kishore Kumar Muchherla, Dung Viet Nguyen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng +2 more | 2024-10-29 |
| 12079517 | Buffer allocation for reducing block transit penalty | Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda +3 more | 2024-09-03 |
| 12068034 | Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming | Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, James Fitzpatrick, Akira Goda +5 more | 2024-08-20 |
| 12051479 | Memory block programming using defectivity information | Kishore Kumar Muchherla, Akira Goda, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley +3 more | 2024-07-30 |
| 12001721 | Multiple-pass programming of memory cells using temporary parity generation | Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Peter Feeley, Sanjay Subbarao, Vivek Shivhare +3 more | 2024-06-04 |
| 11960722 | Memory device programming technique for increased bits per cell | Tomoharu Tanaka, Huai-Yuan Tseng, Dung Viet Nguyen, Kishore Kumar Muchherla, Eric N. Lee +2 more | 2024-04-16 |