Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12079517 | Buffer allocation for reducing block transit penalty | Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda +3 more | 2024-09-03 |
| 12051479 | Memory block programming using defectivity information | Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu +3 more | 2024-07-30 |
| 12001721 | Multiple-pass programming of memory cells using temporary parity generation | Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao +3 more | 2024-06-04 |
| 11995345 | Plane balancing in a memory system | John J. Kane, Byron D. Harris | 2024-05-28 |